1. Field of Invention
The present invention relates to a substrate board structure. More particularly, the present invention relates to the substrate board of a lead-on-chip (LOC) package.
2. Description of Related Art
As semiconductor manufacturing passes into the deep submicron scale, dimensions of each semiconductor device shrink. Hence, each integrated circuit has a higher operating speed. Due to the large-scale miniaturization of devices, volume of a semiconductor package can be reduced. To reduce the size of a semiconductor package, the semiconductor industry has developed several types of package structures such as the lead-on-chip (LOC) or the chip-on-lead (COL). The silicon chip of these package structures is stacked directly on top of the conductive wires of a lead frame or a substrate board. Hence, there is no need to set aside a specific area for mounting the silicon chip, thereby reducing the volume of the package. Other methods of decreasing package volume include the use of a laminated substrate carrier for supporting the silicon chip and the formation of an area array for solder balls.
FIG. 1 is a schematic top view showing a conventional LOC substrate board. The substrate board 10 consists of copper layers and an insulation layer 12 stacked together and having a slot 11 in the middle. After a hole-drilling operation and a copper layer patterning operation, circuit lines 14 are formed on the substrate board surface for subsequent electrical connection with a chip. Each circuit line 14 is also connected to a bonding pad 16 and a ball pad 18. Each bonding pad 16 is an area where the end of a conductive wire is bonded using a wire-bonding machine and each ball pad 18 is an area where a solder ball is attached. A solder mask 20 is formed over the substrate board 10 such that the bonding pads 16 and the ball pads 18 are exposed. In general, copper is used to form the circuit lines 14. However, the surface of a copper layer can be easily oxidized to form a poor conductive layer. Therefore, to increase bondability of each bonding pads 16 with a conductive wire during a wire-bonding operation and each solder ball with a ball pad 18, a layer of gold is usually plated on top.
To facilitate the electroplating of a gold film over the bonding pads 16 and the ball pads 18, additional electroplating bars 22 are formed on the substrate board 10 connecting to all circuit lines 14. After the electroplating bars 22 are appropriately connected to an electrode, electroplating gold can be carried out. However, before carrying out an open/short test (O/S test), electrical connections between the circuit lines 14 must be severed. To maintain substrate board integrity so that subsequent testing and packaging can be conveniently carried out, junctions between the circuit lines 14 and the electroplating bars 22 have to be cut by performing multiple half drillings. The process is laborious and time-consuming. In addition, the electroplating bars are positioned along the peripheral section of a substrate board. Hence, the required board area is increased, leading to a waste of board material.
FIG. 2 is a schematic top view of another conventional substrate board. As shown in FIG. 2, the electroplating bar 22 is different from the one in FIG. 1. The electroplating bar 22 is located in the middle of the slot region 11. The slot 11 is only made after the electroplating operation. In the slot-making process, electrical connections between the electroplating bar 22 and the circuit lines 14 are cut. FIG. 3 is a magnified view of the area surrounding the slot 11 in FIG. 2. As shown in FIG. 3, when the electroplating bar 22 is formed in the middle of the slot region, burrs 24 are likely to form on the edges of the cut surfaces. Hence, some of the circuit lines 14 may be short-circuited leading to poor product quality.